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data sheet powerpc 403gb 32-bit risc embedded controller features ? powerpc ? risc cpu and instruction set architecture ? glueless interfaces to dram, sram, rom, and peripherals, including byte and half-word devices ? separate instruction cache and write-back data cache, both two-way set-associative ? minimized interrupt latency ? individually programmable on-chip control- lers for: Ctwo dma channels Cdram, sram, and rom banks Cperipherals Cexternal interrupts ? flexible interface to external bus masters ? hardware multiplier and divider for faster integer arithmetic ? thirty-two 32-bit general purpose registers applications ? set-top boxes ? consumer electronics and video games ? telecommunications and networking ? office automation (printers, copiers, fax machines) specifications ? 28mhz operation ? interfaces to both 3v and 5v technologies ? low-power 3.3v operation with built-in power management and stand-by mode ? low-cost 128 lead tqfp package ? 0.5 m m triple-level-metal cmos overview the powerpc 403gb 32-bit risc embedded controller offers high performance and functional integration with low power consumption. the 403gb risc cpu executes at sustained speeds approaching one cycle per instruction. on-chip caches and integrated dram and sram control functions reduce chip count and design complex- ity in systems, while improving system through- put. external i/o devices or sram/dram memory banks can be directly attached to the 403gb bus interface unit (biu). interfaces for up to six mem- ory banks and i/o devices, including a maximum of two dram banks, can be configured individu- ally, allowing the biu to manage devices or memory banks with differing control, timing, or bus width requirements. risc execution unit cache unit instruction cache unit data 2-channel dma controller port jtag dram controller i/o controller bus interface unit sram, rom, i/o controls controls address bus data bus timers (address and control) dram interrupt controller
ibm powerpc 403gb 2 the 403gb risc controller consists of a pipe- lined risc processor core and several peripheral interface units: biu, dma controller, asynchro- nous interrupt controller, and jtag debug port. the risc processor core includes the internal 2kb instruction cache and 1kb data cache, reducing overhead for data transfers to or from external memory. the instruction queue logic manages branch prediction, folding of branch and condition register logical instructions, and instruction prefetching to minimize pipeline stalls. risc cpu the risc core comprises three tightly coupled functional units: the execution unit (exu), the data cache unit (dcu), and the instruction cache unit (icu). each cache unit consists of a data array, tag array, and control logic for cache man- agement and addressing. the execution unit consists of general purpose registers (gpr), special purpose registers (spr), alu, multiplier, divider, barrel shifter, and the control logic required to manage data flow and instruction execution within the exu. the exu handles instruction decoding and exe- cution, queue management, branch prediction, and branch folding. the instruction cache unit passes instructions to the queue in the exu or, in the event of a cache miss, requests a fetch from external memory through the bus interface unit. general purpose registers data transfers to and from the exu are handled through the bank of 32 gprs, each 32 bits wide. load and store instructions move data operands between the gprs and the data cache unit, except in the cases of noncacheable data or cache misses. in such cases the dcu passes the address for the data read or write to the biu. when noncacheable operands are being trans- ferred, data can pass directly between the exu and the biu, which interfaces to the external memory being accessed. special purpose registers special purpose registers are used to control debug facilities, timers, interrupts, the protection mechanism, memory cacheability, and other architected processor resources. sprs are accessed using move to/from special purpose register (mtspr/mfspr) instructions, which move operands between gprs and sprs. supervisory programs can write the appropriate sprs to configure the operating and interface modes of the execution unit. the condition regis- ter (cr) and machine state register (msr) are written by internal control logic with program exe- cution status and machine state, respectively. status of external interrupts is maintained in the external interrupt status register (exisr). fixed- point arithmetic exception status is available from the exception register (xer). device control registers device control registers (dcr) are used to man- age i/o interfaces, dma channels, sram and dram memory configurations and timing, and status/address information regarding bus errors. dcrs are accessed using move to/from device control register (mtdcr/mfdcr) instructions, which move operands between gprs and dcrs. instruction set table 1 summarizes the 403gb instruction set by categories of operations. most instructions exe- cute in a single cycle, with the exceptions of load/ store multiple, load/store string, multiply, and divide instructions. bus interface unit the bus interface unit integrates the functional controls for data transfers and address opera- tions other than those which the dma controller handles. dma transfers use the address logic in the biu to output the memory addresses being accessed. control functions for direct-connect i/o devices and for dram, sram, or rom banks are pro- vided by the biu. burst access for sram, rom, and page-mode dram devices is supported for cache fill and flush operations. the biu controls the transfer of data between the external bus and the instruction cache, the data cache, or registers internal to the processor core. the biu also arbitrates among external bus mas- ter and dma transfers, the internal buses to the
ibm powerpc 403gb 3 cache units and the register banks . memory addressing regions the 403gb can address an effective range of 3.192 gb (128 mb dram; 64 mb sram, rom or other i/o; and 3gb reserved). sram banks can be up to 16mb and dram banks for inter- nally multiplexed access can be up to 64mb . cacheability with respect to the instruction or data cache is programmed via the instruction and data cache control registers, respectively. within the dram and sram/rom regions, a total of six banks of devices are supported. each bank can be configured for 8-, 16-, or 32-bit devices. for individual dram banks, the number of wait states, bank size, ras -to- cas timing, use of an external address multiplexer (for external bus masters), and refresh rate are user-programma- ble. for each sram/rom bank, the bank size, bank location, number of wait states, and timings of chip selects, byte enables, and output enables are all user-programmable. instruction cache unit the instruction cache unit (icu) is a two-way set- associative 2 kb cache memory unit with enhancements to support branch prediction and folding. the icu is organized as 64 sets of 2 lines, each line containing 16 bytes. a separate bypass path is available to handle cache-inhib- ited instructions and to improve performance dur- ing line fill operations. the cache can send two cached instructions per cycle to the execution unit, allowing instructions to be folded out of the queue without interrupting normal instruction flow. when a branch instruc- tion is folded and executed in parallel with another instruction, the icu provides two more instructions to replace both of the instructions just executed so that bandwidth is balanced between the icu and the execution unit. data cache unit the data cache unit is provided to minimize the access time of frequently used data items in main store. the 1 kb cache is organized as a two-way set associative cache. there are 32 sets of 2 lines, each line containing 16 bytes of data. the cache features byte-writeability to improve the performance of byte and halfword store opera- tions. cache operations are performed using a write- back strategy. a write-back cache only updates locations in main storage that corresponds to changed locations in the cache. data is flushed from the cache to main storage whenever changed data needs to be removed from the table 1. 403gb instructions by category category base instructions data movement load, store arithmetic / logical add, subtract, negate, multiply, divide, and, or, xor, nand, nor, xnor, sign extension, count leading zeros comparison compare, compare logical, compare immediate branch branch, branch conditional condition condition register logical rotate/shift rotate, rotate and mask, shift left, shift right cache control invalidate, touch, zero, flush, store interrupt control write to external interrupt enable bit, move to/from machine state register, return from interrupt, return from critical interrupt processor management system call, synchronize, move to/from device control registers, move to/ from special purpose registers
ibm powerpc 403gb 4 cache to make room for other data. the data cache may be disabled for a 128mb memory region via control bits in the data cache control register. a separate bypass path is avail- able to handle cache-inhibited data operations and to improve performance during line fill opera- tions. cache flushing and filling are triggered by load, store, and cache control instructions executed by the processor. cache blocks are loaded starting at the requested fullword, continuing to the end of the block and then wrapping around to fill the remaining fullwords at the beginning of the block. dma controller the two-channel dma controller manages block data transfers in buffered, fly-by and memory-to- memory transfer modes with options for burst- mode operation. in fly-by and buffered modes, the dma controller supports transactions between memory and peripheral devices. each dma channel provides a control register, a source address register, a destination address register, a transfer count register, and a chained count register. peripheral set-up cycles, wait cycles, and hold cycles can be programmed into each dma channel control register. each chan- nel supports chaining operations. the dma sta- tus register holds the status of both channels. exception handling table 2 summarizes the 403gb exception priori- ties, types, and classes. exceptions are gener- ated by interrupts from internal and external peripherals, instructions, the internal timer facility, debug events or error conditions. six external interrupt signals are provided on the 403gb: one critical and five general-purpose, all individually maskable. all exceptions fall into three basic classes: asyn- chronous imprecise exceptions, synchronous precise exceptions, and asynchronous precise exceptions. asynchronous exceptions are caused by events external to processor execu- tion, while synchronous exceptions are caused by instructions. except for a system reset or machine check, all 403gb exceptions are handled precisely. pre- cise handling implies that the address of the excepting instruction (synchronous exceptions other than system call) or the address of the next sequential instruction (asynchronous exceptions and system call) is passed to the exception han- dling routine. precise handling also implies that all instructions prior to the excepting instruction have completed execution and have written back their results. asynchronous imprecise exceptions include sys- tem resets and machine checks. synchronous precise exceptions include most debug excep- tions, program exceptions, protection violations, system calls, and alignment error exceptions. asynchronous precise exceptions include the critical interrupt exception, external interrupts, and internal timer facility exceptions and some debug events. only one exception is handled at a time. if multi- ple exceptions occur simultaneously, they are handled in priority order. the 403gb processes exceptions as reset, criti- cal, or noncritical. four exceptions are defined as critical: machine check exceptions, debug excep- tions, exceptions caused by an active level on the critical interrupt pin, and the first time-out from the watchdog timer. when a noncritical exception is taken, special purpose register save/restore 0 (srr0) is loaded with the address of the excepting instruc- tion (synchronous exceptions other than system call) or the next sequential instruction to be pro- cessed (asynchronous exceptions and system call). if the 403gb is executing a multicycle instruction (load/store multiple, load/store string, multiply or divide), the instruction is terminated and its address stored in srr0. save/restore register 1 (srr1) is loaded with the contents of the machine state register. the msr is then updated to reflect the new context of the machine. the new msr contents take effect beginning with the first instruction of the excep- tion handling routine. at the end of the exception handling routine, exe- cution of a return from interrupt (rfi) instruction forces the contents of srr0 and srr1 to be
ibm powerpc 403gb 5 loaded into the program counter and the msr, respectively. execution then begins at the address in the program counter. the four critical exceptions are processed in a similar manner. when a critical exception is taken, srr2 and srr3 hold the next sequential address to be processed when returning from the exception and the contents of the machine state register, respectively. after the critical exception handling routine, return from critical interrupt (rfci) forces the contents of srr2 and srr3 to be loaded into the program counter and the msr, respectively. timers the 403gb contains four timer functions: a time base, a programmable interval timer (pit), a fixed interval timer (fit), and a watchdog timer. the time base is a 56 -bit counter incremented at the timer clock rate. the timer clock is driven by an internal signal equal to the processor clock rate. no interrupts are generated when the time base rolls over. the programmable interval timer is a 32-bit regis- ter that is decremented at the same rate as the time base is incremented. the user preloads the pit register with a value to create the desired delay. when the register is decremented to zeros, the timer stops decrementing, a bit is set in the timer status register (tsr), and a pit inter- rupt is generated. optionally, the pit can be pro- grammed to reload automatically the last value written to the pit register, after which the pit begins decrementing again.the timer control register (tcr) contains the interrupt enable for the pit interrupt. the fixed interval timer generates periodic inter- rupts based on selected bits in the time base. users may select one of four intervals for the timer period by setting the correct bits in the tcr. when the selected bit in the time base changes from 0 to 1, a bit is set in the tsr and a fit interrupt is generated. the fit interrupt enable is contained in the tcr. the watchdog timer generates a periodic inter- rupt based on selected bits in the time base. users may select one of four time periods for the interval and the type of reset generated if the watchdog timer expires twice without an interven- ing clear from software. if enabled, the watchdog timer generates a system reset unless an excep- tion handler updates the watchdog timer status bit before the timer has completed two of the selected timer intervals. jtag port the jtag port has been enhanced to allow it to be used as a debug port. through the jtag test access port, debug software on a workstation can single-step the processor and interrogate internal processor state to facilitate software table 2. 403gb exception priorities, types and classes priority exception type exception class 1 system reset asynchronous imprecise 2 machine check asynchronous imprecise 3 debug synchronous precise (except ude and exc) 4 critical interrupt asynchronous precise 5 watchdogtimer time-out asynchronous precise 6 program exception, protection violation, and system calls synchronous precise 7 alignment exceptions synchronous precise 8 external interrupts asynchronous precise 9 fixed interval timer asynchronous precise 10 programmable interval timer asynchronous precise
ibm powerpc 403gb 6 debugging. the standard jtag boundary-scan register allows testing of circuitry external to the chip, primarily the board interconnect. alterna- tively, the jtag bypass register can be selected when no other test data register needs to be accessed during a board-level test operation. p/n code notes: 1. the dash number indicates the speed version. 2. the characters in the dash number indicate package type (k), revision level (a), commercial version (c). table 3. ppc403gb part number mhz part number 28 PPC403GB-KA28C-1
ibm powerpc 403gb 7 logic symbol signals in brackets are multiplexed.. ppc403gb sysclk holdreq holdack busreq/ int0[testc] int4 error bootw cint reset ready dmar0 xreq dmaa0 xack eot0 [tc0 ] eot1 [tc1 ] wbe0 [a6] wbe3 [a31] oe [xsize1] r/w cs0 cs3 cs6 [ras1] cs7 [ras0] cas0 cas3 amuxcas tck tms tdi tdo dramoe dramwe d0 d31 a8 a29 halt ? ? ? ? ? ? ? ? ? ? risc controller address bus data bus ? ? external master interrupts jtag dram controls sram/dram controls sram controls dma controls wbe1 [a7] wbe2 [a30] dmar1 dmaa1 int1[testd] xsize0 [dmadxfer] int2 int3
ibm powerpc 403gb 8 pin functional descriptions active-low signals are shown with overbars: dmar 0 . multiplexed signals are alphabetized under the first (unmultiplexed) signal names on the same pins. the logic symbol on the preceding page shows all 403gb signals arranged by functional groups. table 4. 403gb signal descriptions signal name pin i/o type function a8 79 i/o address bus bit 8. when the 403gb is bus master, this is an address output from the 403gb . when the 403gb is not bus mas- ter, this is an address input from th e e xternal bus master, to deter- mine bank register usage. a9 80 i/o address bus bit 9. see description of a 8 a10 81 i/o address bus bit 10. see description of a 8 a11 82 i/o address bus bit 11. see description of a 8 a12 83 o address bus bit 12. when the 403gb is bus master, this is an address output from the 403gb . a13 86 o address bus bit 13 . see description of a12. a14 87 o address bus bit 14 . see description of a12. a15 88 o address bus bit 15 . see description of a12. a16 89 o address bus bit 16 . see description of a12. a17 90 o address bus bit 17 . see description of a12. a18 92 o address bus bit 18 . see description of a12. a19 93 o address bus bit 19 . see description of a12. a20 94 o address bus bit 20 . see description of a12. a21 95 o address bus bit 21 . see description of a12. a22 96 i/o address bus bit 22. when the 403gb is bus master, this is an address output from the 403gb . when the 403gb is not bus mas- ter, this is an address input from th e e xternal bus master, to deter- mine page crossings . a23 97 i/o address bus bit 23. see description of a 8
ibm powerpc 403gb 9 a24 98 i/o address bus bit 24. see description of a8 a25 99 i/o address bus bit 25. see description of a8 a26 101 i/o address bus bit 26. see description of a8 a27 102 i/o address bus bit 27. see description of a8 a28 103 i/o address bus bit 28. see description of a8 a29 104 i/o address bus bit 29. see description of a8 amuxcas 127 o dram external address multiplexer select. amuxcas controls the select logic on an external multiplexer. if amuxcas is low, the multiplexer should select the row address for the dram and when amuxcas is 1, the multiplexer should select the column address. bootw 23 i boot-up rom width select. bootw is sampled before and after the reset pin is active to determine the width of the boot-up rom. if this pin is tied to logic 0 when sampled on reset, an 8-bit boot width is assumed. if bootw is tied to 1, a 32-bit boot width is assumed. for 16-bit boot widths, this pin should be tied to the reset pin. busreq/ dmadxfer 123 o bus request. while holdack is active, busreq is active when the 403gb has a bus operation pending and needs to regain control of the bus. dma data transfer. when holdack is not active, dmadxfer indicates a valid data transfer cycle. for dma use, dmadxfer controls burst-mode fly-by dma transfers between memory and peripherals. dmadxfer is not meaningful unless a dma acknowl- edge signal (dmaa0:dmaa1) is active. for transfer rates slower than one transfer per cycle, dmadxfer is active for one cycle when one transfer is complete and the next one starts. for transfer rates of one transfer per cycle, dmadxfer remains active throughout the transfer. cas0 116 o dram column address select 0. cas0 is used with byte 0 of all dram banks. cas1 117 o dram column address select 1. cas1 is used with byte 1 of all dram banks. cas2 118 o dram column address select 2. cas2 is used with byte 2 of all dram banks. table 4. 403gb signal descriptions (continued) signal name pin i/o type function
ibm powerpc 403gb 10 cas3 119 o dram column address select 3. cas3 is used with byte 3 of all dram banks. cint 34 i critical interrupt. to initiate a critical interrupt, the user must main- tain a logic 0 on the cint pin for a minimum of one sysclk clock cycle followed by a logic 1 on the cint pin for at least one sysclk cycle. cs0 8 o sram chip select 0. bank register 0 controls an sram bank, cs0 is the chip select for that bank. cs1 5 o sram chip select 1. same function as cs0 but controls bank 1. cs2 4 o sram chip select 2. same function as cs0 but controls bank 2. cs3 3 o sram chip select 3. same function as cs0 but controls bank 3. cs6 /ras1 2 o chip select 6/ dram row address select 1. when bank register 6 is configured to control an sram bank, cs6 /ras1 functions as a chip select. when bank register 6 is configured to control a dram bank, cs6 /ras1 is the row address select for that bank. cs7 /ras0 128 o chip select 7/ dram row address select 0. same function as cs6 /ras1 but controls bank 7. d0 36 i/o data bus bit 0 (most significant bit) d1 37 i/o data bus bit1 d2 39 i/o data bus bit 2 d3 40 i/o data bus bit 3 d4 41 i/o data bus bit 4 d5 43 i/o data bus bit 5 d6 44 i/o data bus bit 6 d7 45 i/o data bus bit 7 d8 46 i/o data bus bit 8 d9 47 i/o data bus bit 9 d10 48 i/o data bus bit 10 table 4. 403gb signal descriptions (continued) signal name pin i/o type function
ibm powerpc 403gb 11 d11 49 i/o data bus bit 11 d12 50 i/o data bus bit 12 d13 53 i/o data bus bit 13 d14 54 i/o data bus bit 14 d15 57 i/o data bus bit 15 d16 58 i/o data bus bit 16 d17 59 i/o data bus bit 17 d18 60 i/o data bus bit 18 d19 61 i/o data bus bit 19 d20 62 i/o data bus bit 20 d21 63 i/o data bus bit 21 d22 64 i/o data bus bit 22 d23 67 i/o data bus bit 23 d24 68 i/o data bus bit 24 d25 69 i/o data bus bit 25 d26 70 i/o data bus bit 26 d27 71 i/o data bus bit 27 d28 72 i/o data bus bit 28 d29 73 i/o data bus bit 29 d30 74 i/o data bus bit 30 d31 75 i/o data bus bit 31 dmaa0 9 o dma channel 0 acknowledge. dmaa0 has an active level when a transaction is taking place between the 403gb and a peripheral. dmaa1 10 o dma channel 1 acknowledge. see description of d maa0 table 4. 403gb signal descriptions (continued) signal name pin i/o type function
ibm powerpc 403gb 12 dmar0 15 i dma channel 0 request. when the 403gb is the bus master, external devices request a dma transfer on channel 0 by putting a logic 0 on dmar0 . when the 403gb holdack output is active and the 403gb is not the bus master, active requests on dmar0 are ignored until the 403gb becomes the bus master. dmar1 16 i dma channel 1 request. see description of dmar0 dramoe 125 o dram output enable. dramoe has an active level when either the 403gb or an external bus master is reading from a dram bank. this signal enables the selected dram bank to drive the data bus. dramwe 126 o dram write enable. dramwe has an active level when either the 403gb or an external bus master is writing to a dram bank. eot0 /tc0 112 i/o end of transfer 0 / terminal count 0. the function of the eot0 / tc0 is controlled via the eot /tc bit in the dma channel 0 control register. when eot0 /tc0 is configured as an end of transfer pin, external users may stop a dma transfer by placing a logic 0 on this input pin. when configured as a terminal count pin, the 403gb signals the completion of a dma transfer by placing a logic 0 on this pin. eot1 /tc1 113 i/o end of transfer1 / terminal count 1. see description of e ot0 /tc0 error 124 o system error. error goes to a logic 1 whenever a machine check error is detected in the 403gb. the error pin then remains a logic 1 until the machine check error is cleared in the exception syndrome register and/or bus error syndrome register. gnd 1 ground. all ground pins must be used. 6 ground. all ground pins must be used. 20 ground. all ground pins must be used. 38 ground. all ground pins must be used. 51 ground. all ground pins must be used. 55 ground. all ground pins must be used. 66 ground. all ground pins must be used. table 4. 403gb signal descriptions (continued) signal name pin i/o type function
ibm powerpc 403gb 13 gnd 76 ground. all ground pins must be used. 84 ground. all ground pins must be used. 100 ground. all ground pins must be used. 115 ground. all ground pins must be used. 120 ground. all ground pins must be used. halt 22 i halt from external debugger, active low. holdack 122 o hold acknowledge. holdack outputs a logic 1 when the 403gb relinquishes its external buses to an external bus master. the exter- nal bus master uses the holdreq pin to request use of the 403gb buses. holdreq 25 i hold request. external bus masters can request the 403gb bus by placing a logic1 on this pin. when the 403gb holdack pin is logic 1, the 403gb has relinquished its address, data and control buses to the external master. the external bus master relinquishes the buses to the 403gb by deasserting holdreq. the 403gb then deasserts holdack during the following cycle. int0/testc 29 i interrupt 0. while reset is not active, int0 is an interrupt input to the 403gb and users may program the pin to be either edge-trig- gered or level triggered and may also program the polarity to be active high or active low. the iocr contains the bits necessary to program the trigger type and polarity. testc. reserved for manufacturing test during the reset interval. while reset is active, this signal should be tied low for normal oper- ation. int1/testd 30 i interrupt 1 / testd. see description of int0/testc. int2 31 i interrupt 2. int2 is an interrupt input to the 403gb and users may program the pin to be either edge-triggered or level triggered and may also program the polarity to be active high or active low. the iocr contains the bits necessary to program the trigger type and polarity. int3 32 i interrupt 3. see description of int2 int4 33 i interrupt 4. see description of int2 table 4. 403gb signal descriptions (continued) signal name pin i/o type function
ibm powerpc 403gb 14 ivr 35 interface voltage reference. when connected to 3.3v supply, allows the device to interface to an exclusively 3v system. when connected to 5v supply, allows the device to interface to 5v or mixed 3v/5v system. if any input or output connects to 5v system, this pin must be connected to 5v supply. oe / xsize1 110 o/i output enable / external master transfer size 1. when the 403gb is bus master, oe enables the selected srams to drive the data bus. the timing parameters of oe relative to the chip select, cs , are programmable via bits in the 403gb bank registers. when the 403gb is not bus master, oe / xsize1 is used as one of two external transfer size input bits, xsize0:1. ready 24 i ready. ready is used to insert externally generated (device- paced) wait states into bus transactions. the ready pin is enabled via the ready enable bit in 403gb bank registers. reset 78 i/o reset. a logic 0 input placed on this pin for eight sysclk cycles causes the 403gb to begin a system reset. when a system reset is internally invoked, the reset pin becomes a logic 0 output for three sysclk cycles, and the system must maintain reset active for a total of eight cycles minimum. r/w 111 i/o read / write. when the 403gb is bus master, r/w is an output which is high when data is read from memory and low when data is written to memory. r/w is driven with the same timings as the address bus. when the 403gb is not bus master, r/w is an input from the exter- nal bus master which indicates the direction of data transfer. sysclk 26 i sysclk is the processor system clock input. sysclk supports a 50/ 50 duty cycle clock input at the rated chip frequency. tck 18 i jtag test clock input. tck is the clock source for the 403gb test access port (tap). the maximum clock rate into the tck pin is one half of the processor sysclk clock rate. tdi 13 i test data in. the tdi is used to input serial data into the tap. when the tap enables the use of the tdi pin, the tdi pin is sam- pled on the rising edge of tck and this data is input to the selected tap shift register. tdo 12 o test data output. tdo is used to transmit data from the 403gb tap. data from the selected tap shift register is shifted out on tdo. testa 27 i reserved for manufacturing test. tied low for normal operation. table 4. 403gb signal descriptions (continued) signal name pin i/o type function
ibm powerpc 403gb 15 testb 28 i reserved for manufacturing test. tied high for normal operation. tms 21 i test mode select. the tms pin is sampled by the tap on the ris- ing edge of tck. the tap state machine uses the tms pin to determine the mode in which the tap operates. v dd 7 power. all power pins must be connected to 3.3v supply. 19 power. all power pins must be connected to 3.3v supply. 42 power. all power pins must be connected to 3.3v supply. 52 power. all power pins must be connected to 3.3v supply. 56 power. all power pins must be connected to 3.3v supply. 65 power. all power pins must be connected to 3.3v supply. 77 power. all power pins must be connected to 3.3v supply. 85 power. all power pins must be connected to 3.3v supply. 91 power. all power pins must be connected to 3.3v supply. 105 power. all power pins must be connected to 3.3v supply. 114 power. all power pins must be connected to 3.3v supply. 121 power. all power pins must be connected to 3.3v supply. wbe0 / a6 106 o/i write byte enable 0 / address bus bit 6. when the 403gb is bus master, the write byte enable outputs, wbe0:3 , select the active byte(s) in a memory write access. for 8-bit memory regions, wbe2 and wbe3 become address bits 30 and 31 and wbe0 is the write- enable line. for 16-bit memory regions, wbe2 :wbe3 are address bits a30:a31 and wbe0 and wbe1 are the high byte and low write enables, respectively. for 32-bit memory regions, wbe0:3 are write byte enables for bytes 0-3 on the data bus, respectively. when the 403gb is not bus master, wbe0:1 are used as the a6:7 inputs (for bank register selection) and wbe2:3 are used as the a30:31 inputs (for byte selection and page crossing detection). wbe1 / a7 107 o/i write byte enable 1 / address bus bit 7. see description of wbe0 / a6 above. table 4. 403gb signal descriptions (continued) signal name pin i/o type function
ibm powerpc 403gb 16 wbe2 / a30 108 o/i write byte enable 2 / address bus bit 30. see description of wbe0 / a6 above wbe3 / a31 109 o/i write byte enable 3 / address bus bit 31. see description of wbe0 / a6 above xack 11 o when the 403gb holdack output is active and the 403gb is not bus master, xack is an output from the 403gb which has an active level when data is valid during an external bus master trans- action. xreq 17 i when the 403gb is not the bus master, the external bus master places a logic 0 on xreq when the 403gb holdack is active and external bus master wishes to initiate a transfer to the dram con- trolled by the 403gb dram controller. xsize0 14 i external master transfer size 0. when the 403gb is not bus master, xsize0 is used as one of two external transfer size input bits, xsize0:1. table 4. 403gb signal descriptions (continued) signal name pin i/o type function
ibm powerpc 403gb 17 table 5. signals ordered by pin number pin signal names pin signal names pin signal names pin signal names 1 gnd 33 int4 65 v dd 97 a23 2 cs6 /ras1 34 cint 66 gnd 98 a24 3 cs3 35 ivr 67 d23 99 a25 4 cs2 36 d0 68 d24 100 gnd 5 cs1 37 d1 69 d25 101 a26 6 gnd 38 gnd 70 d26 102 a27 7v dd 39 d2 71 d27 103 a28 8 cs0 40 d3 72 d28 104 a29 9 dmaa0 41 d4 73 d29 105 v dd 10 dmaa1 42 v dd 74 d30 106 wbe0 / a6 11 xack 43 d5 75 d31 107 wbe1 / a7 12 tdo 44 d6 76 gnd 108 wbe2 / a30 13 tdi 45 d7 77 v dd 109 wbe3 / a31 14 xsize0 46 d8 78 reset 110 oe / xsize1 15 dmar0 47 d9 79 a8 111 r/w 16 dmar1 48 d10 80 a9 112 eot0 /tc0 17 xreq 49 d11 81 a10 113 eot1 /tc1 18 tck 50 d12 82 a11 114 v dd 19 v dd 51 gnd 83 a12 115 gnd 20 gnd 52 v dd 84 gnd 116 cas0 21 tms 53 d13 85 v dd 117 cas1 22 halt 54 d14 86 a13 118 cas2 23 bootw 55 gnd 87 a14 119 cas3 24 ready 56 v dd 88 a15 120 gnd 25 holdreq 57 d15 89 a16 121 v dd 26 sysclk 58 d16 90 a17 122 holdack 27 testa 59 d17 91 v dd 123 busreq/ dmadxfer 28 testb 60 d18 92 a18 124 error 29 int0/testc 61 d19 93 a19 125 dramoe 30 int1/testd 62 d20 94 a20 126 dramwe 31 int2 63 d21 95 a21 127 amuxcas 32 int3 64 d22 96 a22 128 cs7 /ras0
ibm powerpc 403gb 18 tqfp mechanical drawing (top view) index mark 1 38 39 64 65 102 103 128 0.22 0.05 0.009 0.002 0.5 basic 0.0197 dimensions: mm inches 1.6 max 0.063 see detail note: english dimensions are for reference only. 0.05 min 0.002 0 - 7 0.015 0.05 0.006 0.002 0.60 0.15 0.023 0.006 16.0 0.2 0.63 0.008 14 0.2 0.55 0.008 16.0 0.2 0.63 0.008 14.0 0.2 0.55 0.008
ibm powerpc 403gb 19 package thermal specifications the 403gb is design ed to operate within the case temperature range from 0c to 120c. thermal resistance values for the 128 t qfp are shown in table 6 : . notes: 1. case temperature tm c is measured at top center of case surface with device soldered to circuit board . 2. t m a = tm c C p q ca , where tm a is ambient tem- perature . 3. t m cmax = tm jmax C p q jc , where tm jmax is maxi- mum junction temperature and p is power con- sumption. 4. t he above assumes that the chip is mounted on a card with at least one signal and two power planes. electrical specifications absolute maximum ratings the absolute maximum ratings in table 7 below are stress ratings only. operation at or beyond these maximum ratings may cause permanent damage to the device. operating conditions the 403gb can interface to either 3v or 5v tech- nologies. the range for supply voltages is speci- fied for five-percent margins relative to a nominal 3.3v power supply. device operation beyond the conditions specified in table 8 is not recommended. extended opera- tion beyond the recommended conditions may affect device reliability: power considerations power dissipation is determined by operating fre- quency, temperature, and supply voltage, as well as external source/sink current requirements. typical power dissipation is 0.21 w at 28 mhz, tm c = 55 c, and v cc = 3.3 v, with an average 10pf capacitive load. estimated supply current as a function of fre- quency is shown in the figure, " supply current vs operating frequency ," on page 28. derating curves are provided in the section, " output der- ating for capacitance and voltage ," on page 25. recommended connections power and ground pins should all be connected to separate power and ground planes in the cir- cuit board to which the 403gb is mounted. unused input pins must be tied inactive, either high or low. the interface voltage reference (ivr) pin should be connected to 3.3v supply if all signal pins con- necting to the 403gb pins operate at 3v levels. if any signal pin connecting to the 403gb oper- ates with 5v levels, the ivr pin should be con- nected to 5v supply. table 6. thermal resistance (c/watt) parameter airflow-ft/min (m/sec) 0 (0) 100 (0.51) 200 (1.02) q jc junction to case 2 2 2 q ca case to ambient (without heatsink) 37 29 28 table 7. 403gb maximum ratings parameter maximum rating supply voltage with respect to gnd -0.5v to +3.8v voltage on other pins with respect to gnd -0.5v to +5 .5v case temperature under bias 0c to +120c storage temperature -65 c to +150c table 8. operating conditions symbol parameter min max unit v dd supply voltage 3.14 3.47 v f c clock frequency 0 28 mhz tm c case tempera- ture under bias -40 85 c
ibm powerpc 403gb 20 dc specifications notes: 1. v ivr is the interface voltage reference to which the ivr pin is tied to select either a 3.3v or 5v interface. for addi- tional information, see "recommended connections," on page 19. 2. the 403gb drives its outputs to the level of v dd and, when not driving, the 403gb outputs can be pulled up to 5v by other devices in a system if the 403gb ivr pin has been tied to 5v properly. 3. i cc max is measured at tm c = 85 c , worst-case recommended operating conditions for frequency and voltage as specified in table 8 on page 19, and a capacitive load of 50 pf. note: 1. c out is specified as the load capacitance of a floating output in high impedance. ac specifications clock timing and switching characteristics are specified in accordance with recommended operating conditions in table 8. ac specifications are tested at v dd = 3.14v and t j = 85c with the 50pf test load shown in the figure at right. derating of outputs for capacitive loading is shown in the figure "output derating for capacitance and voltage," on page 25. table 9. 403gb dc characteristics symbol parameter min max units v il input low voltage (except for sysclk) gnd - 0.1 0.8 v v ilc input low voltage for sysclk gnd - 0.1 0.8 v v ih input high voltage (except for sysclk) 1 2.0 v ivr + 0.1 v v ihc input high voltage for sysclk 1 2.0 v ivr + 0.1 v v ol output low voltage 0.4 v v oh output high voltage 2.4 v dd v i oh output high current 2 ma i ol output low current 4 ma i li input leakage current 50 m a i lo output leakage current 10 m a i cc supply current (i cc max at f c of 28mhz) 2 210 ma table 10. 403gb i/o capacitance symbol parameter min max units c in input capacitance (except for sysclk) 5 pf c inc input capacitance for sysclk 25 pf c out output capacitance 1 7pf c i/o i/o pin capacitance 8 pf output pin c l c l = 50 pf for all signals
ibm powerpc 403gb 21 sysclk timing notes: 1. cycle-to-cycle jitter allowed between any two edges. 2. rise and fall times measured between 0.8v and 2.0v. table 11. 403gb system clock timing symbol parameter min max units f c sysclk clock input frequency 28 mhz t c sysclk clock period 36 ns t cs clock edge stability 1 0.2 ns t ch clock input high time 16 ns t cl clock input low time 16 ns t cr clock input rise time 2 0.5 2.5 ns t cf clock input fall time 2 0.5 2.5 ns t cr t cf t cl t ch t c 2.0v 1.5v 0.8v
ibm powerpc 403gb 22 input setup and hold waveform notes: 1. the 403gb may be programmed to latch data from the data bus either on the rise of sysclk or the rise of cas . when the 403gb is programmed to latch data on cas , bit 26 of the i/o control register (iocr) is set to 1. 2. t cas2clk 3 15.5 ns. the capacitive load on the cas outputs must not delay the cas low-to-high transition such that the period from the cas rising edge to the next sysclk rising edge becomes less than 15.5 ns. the maximum value of cas capacitive loading can be determined by using the output time for cas from table 16 on page 25, and applying the appropriate derating factor for your application. see the figure, "output derating for capacitance and voltage," on page 25. table 12. 403gb synchronous input timings symbol parameter min max units t is input setup time t is1 t is2 t iscas t is3 t is4 t is5 t is6 t is7 a6:11,a22:31 d0:31 (to sysclk) d0:31 (to cas ) holdreq r/w ready xreq xsize0:1 4 5 2 4 3 6 5 5 ns
ibm powerpc 403gb 23 note: 1. data bus setup and hold times for dram cas mode are measured relative to cas deactivation. notes: 1. during a system-initiated reset, reset must be taken low for a minimum of eight sysclk cycles. 2. the bootw input has a maximum rise time requirement of 10 ns when it is tied to reset . 3. input hold times are measured at 3.47v and t j = 10 c. t ih input hold time t ih1 t ih2 t ihcas t ih3 t ih4 t ih5 t ih6 t ih7 a6:11,a22:31 d0:31 (after sysclk) d0:31 (after cas ) holdreq r/w ready xreq xsize0:1 2 2 3 2 2 2 2 2 ns t r ,t f input rise, fall time 0.5 2.5 ns table 13. 403gb asynchronous input timings symbol parameter min max units t is input setup time t is8 t is9 t is10 t is11 t is12 t is13 cint dmar0:1 eot0:1 halt int0:4 reset 5 3 3 3 6 8 ns t ih input hold time t ih8 t ih9 t ih10 t ih11 t ih12 t ih13 cint dmar0:1 eot0:1 halt int0:4 reset t c t c t c t c t c note 1, 2 ns table 12. 403gb synchronous input timings symbol parameter min max units
ibm powerpc 403gb 24 output delay and float timing waveform table 14. 403gb synchronous output timings symbol parameter t ohmin t ovmax units t oh , t ov output hold, output valid time t oh1 , t ov1 t oh2 , t ov2 t oh3 , t ov3 t oh4 , t ov4 t oh5 , t ov5 t oh6 , t ov6 t oh7 , t ov7 t oh8 , t ov8 t oh9 , t ov9 t oh10 , t ov10 t oh11 , t ov11 t oh12 , t ov12 t oh13 , t ov13 t oh14 , t ov14 t oh15 , t ov15 t oh16 , t ov16 t oh17 , t ov17 t oh18 , t ov18 t oh19 , t ov19 t oh20 , t ov20 a8:31 amuxcas busreq cas0:3 cs0:3,6:7 d0:31 dmaa0:1 dmadxfer dramoe dramwe error holdack oe ras0:1 ras0:3 (early) reset r/w tc0:1 wbe0:3 xack 4 3 3 4 2 4 3 3 3 2 4 3 3 3 12 3 3 3 3 3 15 11 12 13 13 16 11 13 11 10 14 12 11 12 21 14 11 13 12 13 ns valid t ov t oh 1.5v 1.5v 1.5v min outputs sysclk outputs t of min max max 1.5v 1.5v 1.5v
ibm powerpc 403gb 25 notes: 1. for normal ras and cas timing, t oh is relative to the rising edge of sysclk and t ov is relative to the falling edge of sysclk. in early ras mode, t ov is relative to the rising edge of sysclk. cas access time assumes a sysclk 50% duty cycle. 2. in early ras mode, the ras output delay varies with the 403gb operating frequency. use the following equation to determine the worst-case output delay for this signal: t ov max = 12 ns + tc/4; t oh min remains unchanged. valid for t c greater than 30 ns and less than 80 ns. 3. when initiating a system reset, the 403gb pulls the reset output low for 2048 cycles minimum and then samples to determine when reset has gone low . three cycles after reset has been sampled as low, the 403gb stops driv- ing the reset output . at this time the system must hold reset low for five more cycles. 4. output times are measured with a standard 50 pf capacitive load, unless otherwise noted. output hold times are measured at 3.47v and t j = 10 c. output derating for capacitance and voltage t of output float time t of1 t of2 t of3 t of4 t of5 t of6 t of7 a8:31 cs0:3,6:7 d0:31 oe reset r/ w wbe0:3 min 2 3 3 3 2 3 3 max 10 12 11 12 8 12 12 ns t cas available cas access time min max ns 2-1-1-1 access mode (note ) 3-2-2-2 access mode (note ) 0.5t c -2.5 1.5t c -2.5 table 14. 403gb synchronous output timings symbol parameter t ohmin t ovmax units note: test conditions v t = 1.5v at t j = 85c 0 50 100 150 0 -10 +10 +20 d output delay (ns) c l (pf) tp zl d c = 0.14 c l - 1.2ns tp lh d c = 0.04 c l - 1.9ns tp hl d c = 0.06 c l - 2.3ns output propagation delay derating derating equations for output delays: 1. d tp lh (c l , v) = tp lh d c + tp lh d v 2. d tp hl (c l , v) = tp hl d c + tp hl d v 3 . d tp zl5v (c l , v) = tp zl d c + tp hl d v (from 5.5v)
ibm powerpc 403gb 26 output propagation delay derating vs output voltage level output rise and fall time derating 1.5 3 0 0 +2 +4 +6 tp lh d v (c l = 25 pf) tp lh d v (c l = 50pf) tp lh d v (c l = 100 pf) v out (v) note: test condition t j = 85c d output delay (ns) tp hl d v (c l = 100 pf) tp hl d v (c l = 50pf) tp hl d v (c l = 25 pf) note: test conditions v t = 0.8v to 2v at t j = 85c 0 +6 +2 0 50 100 150 +4 -2 d output transition (ns) c l (pf) tp r d c tp f d c output transition time derating 4. t r (c l ) = 2ns + tp r d c 5. t f (c l ) = 2.5ns + tp f d c derating equations for output rise and fall times:
ibm powerpc 403gb 27 output voltage vs output current receiver input voltage vs dc input current note: 1. applies to receivers for asynchronous inputs on pins 15-18, 21-25, 29-34, and 78 , and synchronous inputs on pins 17 and 25 . 3.5 3 2.5 2 3 2 1 0 i ol (ma) 0.6 0.3 0 0 1 2 34 i oh (ma) v oh min (v) v ol max (v) note: test conditions 3.14v at t j = 85c 2.0 2.2 2.4 2.6 0.6 0.4 0.2 0 t j = 25c at 3.47v t j = 85c at 3.14v t j = 25c at 3.47v t j = 85c at 3.14v 100 80 60 40 20 0 v in (v) i in ( m a)
ibm powerpc 403gb 28 receiver noise sensitivity supply current vs operating frequency noise pulse width (ns) note: test conditions 3.14v at t j = 85c 5 4 3 2 1 1 2 345 0 amplitude (v) positive spike negative spike amplitude 50% pulse width 0.4v amplitude pulse width 50% 2.4v i cc (ma) 0 0 210ma 28 f sysclk (mhz) test conditions: 3.47v at t j = 85c 64ma (worst case) test conditions: (typical) 3.3v at t j = 55c
ibm powerpc 403gb 29 reset and holdack the following table summarizes the states of signals on output pins when reset or holdack is active. note : 1. s ignal may be active while holdack is asserted, depending on the operation being performed by the 403gb . bus waveforms the waveforms in this section represent external bus operations, including sram and dram accesses, dma transfers, and external master operations. write byte enable encoding the 403gb provides four write byte enable signals ( wbe0:3 ) to support 8-, 16-, and 32-bit devices, as shown in table 16 . for an eight-bit memory region, wbe2:3 are encoded as a30:31 and wbe0 is the byte-enable line. for a 16-bit region, wbe0 is the high-byte enable, wbe1 is the low-byte enable and wbe2:3 are encoded as a30:31. for a 32-bit region, address bits 8:29 select the word address and wbe0:3 select data bytes 0:3, respectively. table 15. signal states during reset or hold acknowledge signal names state when reset active state when holdack active a8:29 amuxcas busreq cas0:3 floating inactive (low) inactive (low) inactive (high) floating (set to input mode) operable (see note 1) operable (see note 1) operable (see note 1) cs0:3 cs6:7 / ras1:0 d0:31 dmaa0:1 floating floating floating inactive (high) floating cs floating, ras operable (see note 1) floating (external master drives bus) inactive (high) xack dramoe dramwe inactive (high) inactive (high) inactive (high) operable (see note 1) operable (see note 1) operable (see note 1) error holdack oe reset inactive (low) inactive (low) floating floating unless initiating system reset operable (see note 1) active floating (input for xsize1) floating unless initiating system reset r/ w tc0:1 tdo wbe0:3 floating floating (set to input) inactive (high) floating floating (set to input) inactive (high) operable (see note 1) operable (inputs for a6:7, a30:31)
ibm powerpc 403gb 30 address bus multiplexing to support memories and i/o devices with differing configurations and bus widths, the 403gb provides an internally multiplexed address bus controlled by the biu. table 17 shows the multiplexed address out- puts referenced by waveforms later in this section. table 16. write byte enable encoding 8-bit bus width transfer size address wbe0 = we wbe1 = 1 wbe2 = a30 wbe3 = a31 byte00100 byte10101 byte20110 byte30111 16-bit bus width transfer size address wbe0 = bhe wbe1 = ble wbe2 = a30 wbe3 =a31 half-word 0 0000 half-word 2 0010 byte00100 byte11001 byte20110 byte31011 32-bit bus width transfer size address wbe0 wbe1 wbe2 wbe3 word00000 half-word 0 0011 half-word 2 1100 byte00111 byte11011 byte21101 byte31110 table 17. multiplexed address outputs address pins a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 addr bits out in ras cycle a6 a7 a8 a9 a10 a11 a12 a13 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 addr bits out in cas cycle xx a6 a7 a8 a9 a10 a11 a12 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31
ibm powerpc 403gb 31 sram read-write-read with zero wait and one hold bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 18 on page 30 for wbe signal definitions based on bus width. slf burst mode bus width ready enable wait states cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 0 xx 0 00 0000 0 0 0 0 001 a8:29, 1 wbe2 [a30], wbe3 [a31] r/w csx oe wbe0:3 2 d0:31 read address sysclk 1 2 3 4 5 6 7 8 data in data out data in write address read address
ibm powerpc 403gb 32 sram, rom, or i/o write request with wait and hold bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 18 for wbe signal definitions based on bus width. 3. 403gbwait must be programmed to a value 3 (cson + weon + weoff) and 3 (cson + oeon + weoff). if wait > (cson + weon) and > (cson + oeon), then all signals retain the values shown in cycle 4 until the wait time expires. 4. if hold is programmed > 001, all signals retain the values shown in cycle 6 until the hold timer expires. slf burst mode bus width ready enable wait states cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 0 xx 0 00 0011 0 or 1 0 or 1 0 or 1 0 or 1 001 sysclk a8:29, 1 wbe2 [a30], wbe3 [a31] r/w csx 3 oe 3 wbe0:3 2,3 d0:31 address valid data out cson=0 cson=1 cson=0 weon=0 cson=1,0 weon=0,1 cs0n=1 weon=1 wait + 1 cycle hold 4 weoff=1 weoff=0 1 2 3 4 5 6 7 8 cson=0 oeon=0 cson=1,0 oeon=0,1 cs0n=1 oeon=1
ibm powerpc 403gb 33 sram, rom, or i/o read request, wait extended with ready bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 18 on page 30 for wbe signal definitions based on bus width. 3. wait must be programmed to a value 3 (cs on + oe on ). if wait > (cs on + oe on ), then all signals will retain the values shown in cycle 4 until the wait timer expires. 4. if hold is programmed > 001, all 403gb output signals retain the values shown in cycle 7 until the hold timer expires. 5. if wait = 00 0000, the ready input is ignored and single-cycle transfers occur. if wait = 00 000 1 , ready is sampled starting in cycle 2. if wait > 00 0001, ready is sampled starting after the wait cycles have expired. 6. data is captured 1 cycle after ready is sampled active. slf burst mode bus width ready enable wait states cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 0 xx 1 00 0010 0 or 1 0 or 1 0 or 1 x 001 a8:29, 1 wbe2 [a30], wbe3 [a31] r/w csx 3 oe 3 wbe0:3 2,3 d0:31 address valid data in cson=0 cson=1 cson=0 oeon=0 cson=0,1 oeon=1,0 cs0n=1 oeon=1 ready 5 wait not ready not ready sample ready sample data 6 ready hold sysclk 1 2 3 4 5 6 7 8
ibm powerpc 403gb 34 sram, rom or i/o burst read with wait and hold bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 18 on page 30 for wbe signal definitions based on bus width. 3. wait must be programmed to a value 3 (cson + oeon). if wait > (cson + oeon), then all signals will retain the values shown in cycle 3 until the wait timer expires. 4. if hold is programmed > 001, all 403gb output signals retain the values shown in cycle 7 until the hold timer expires. slf burst mode bus width ready enable wait states burst wait cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:21 bits 22:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 1 xx 0 0001 00 0 or 1 0 or 1 x x 001 a8:29, 1 wbe2 [a30], wbe3 [a31] r/w csx 3 oe 3 wbe0:3 2,3 d0:31 cson=0 cson=1 cson=0 oeon=0 cson=0,1 oeon=1,0 sysclk 1 2 3 4 5 6 7 8 address1 addr2 addr3 address4 d1 d2 d3 d4 wait + 1 cycles 3 hold burst + 1 cycles burst + 1 cycles burst + 1 cycles 4
ibm powerpc 403gb 35 sram, rom or i/o burst write with wait, burst wait, and hold bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 18 on page 30 for wbe signal definitions based on bus width. 3. wait must be programmed to a value 3 (cson + weon + weoff) and 3 (cson + oeon + weoff). if wait > (cson + weon) and > (cson + oeon), then all signals retain the values shown in cycle 3 until the wait timer expires. 4. if hold is programmed > 001, all 403gb output signals retain the values shown in cycle 12 until the hold timer expires. slf burst mode bus width ready enable wait states burst wait cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:21 bits 22:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 1 xx 0 0100 01 0 or 1 0 or 1 0 or 1 0 or 1 001 2 3 4 5 6 7 8 9 10 11 12 13 14 1 a8:29, 1 wbe2 [a30], wbe3 [a31] r/w csx 3 oe 3 wbe0:3 2,3 d0:31 sysclk address1 addr2 addr3 address4 data1 data2 data3 data4 wait + 1 cycles hold burst + 1 cycles burst + 1 cycles burst + 1 cycles weon=0,1 weon=0 cson=1,0 cson=0 weon=1 cson=1 weoff=1 weoff=1 weoff=1 weoff=1 weoff=0 cson=1 cson=0 oeon=0,1 oeon=0 cson=1,0 cson=0 cson=1 oeon=1
ibm powerpc 403gb 36 dram 2-1-1-1 page mode read bank register bit settings notes: 1. for burst access, the address represented by columns 1:4 does not necessarily indicate that they are in incremen- tal address order. typically, burst access is target word first. 2. if internal mux mode is used, address bits a11:29 represent address bits described in table 17 on page 30. 3. during internal mux mode access, a8:10 retain their unmultiplexed values. 4. if external mux mode is used, a11:29 are unaffected and do not change between cas and ras cycles. 5. if bus width is programmed as byte or half-word, wbe2:3 represent address bits a30:31 regardless of mux mode. 6. wbe0:1 are always ones during dram transfers. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 xx x 0 0 1 00 00 0 x xxxx 1 2 3 4 5 6 7 8 sysclk a11:29, r/w ras cas0:3 dramoe dramwe d0:31 amuxcas ras cas cas cas cas pre- charge row column2 column3 column4 column1 data1 data2 data3 data4 wbe2 [a30], wbe3 [a31]
ibm powerpc 403gb 37 dram 3-2-2-2 page mode write bank register bit settings notes: 1. for burst access, the addresses represented by columns 1:4 do not necessarily indicate that they are in incre- mental address order. typically, burst access is target word first. 2. if internal mux mode is used, address bits a11:29 represent address bits described in table 17 on page 30. 3. during internal mux mode access, a8:10 retain their unmultiplexed values. 4. if external mux mode is used, a11:29 are unaffected and do not change between cas and ras cycles. 5. if bus width is programmed as byte or half-word, wbe2:3 represent address bits a30:31 regardless of mux mode. 6. wbe0:1 are always ones during dram transfers. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 xx x 0 0 1 01 01 0 x xxxx sysclk a11:29 r/w ras cas0:3 dramoe dramwe d0:31 1 2 3 4 5 6 7 8 9 10 11 12 amuxcas row column1 column2 column3 column4 ras cas cas cas cas pre- charge cas cas cas cas data1 data2 data3 data4
ibm powerpc 403gb 38 dram read-write-read, one wait bank register bit settings notes: 1. if internal mux mode is used, address bits a11:29 represent address bits described in table 17 on page 30. 2. during internal mux mode access, a8:10 retain their unmultiplexed values. 3. if external mux mode is used, a11:29 are unaffected and do not change between cas and ras cycles. 4. if bus width is programmed as byte or half-word, wbe2:3 represent address bits a30:31 regardless of mux mode. 5. wbe0:1 are always ones during dram transfers. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 xx x 0 0 0 01 xx 0 x xxxx sysclk a11:29 r/w ras cas0:3 dramoe dramwe d0:31 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 amuxcas data1 data2 data3 ras cas cas pre- charge ras cas cas pre- charge ras cas cas pre- charge row1 column1 row2 column2 row3 column3
ibm powerpc 403gb 39 dma buffered single transfer from peripheral to 3-cycle dram bank register bit settings dma control register bit settings notes: 1. dmar must be inactive in cycle 9 to guarantee a single transfer. 2. peripheral data bus width must match dram bus width. 3. this waveform assumes that the internal address mux is used. 4. cas0 is used for byte accesses, cas0:1 for halfwords, and cas0:3 for fullwords. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 0 0 0 0 01 xx 0 x xxxx transfer direction transfer width transfer mode peripheralsetup peripheral wait peripheral hold bit 2 bits 4:5 bits 9:10 bits 11:12 bits 13:18 bits 19-21 1 10 00 00 00 0000 000 dmar dmaa a11:29 r/w ras cas0:3 dramoe dramwe d0:31 oe wbe0:3 1 2 3 4 5 6 7 8 9 10 11 12 sysclk sync sync biu req dma ack ras cas cas pre- charge row column data data
ibm powerpc 403gb 40 dma fly-by single transfer, write to 3-cycle dram bank register bit settings dma control register bit settings notes: 1. dmar must be inactive in cycle 7 (last dmaa cycle) to guarantee a single transfer. 2. peripheral data bus width must match dram bus width. 3. see diagram for settings. 4. this waveform assumes that the internal address mux is used. 5. cas0 is used for byte accesses, cas0:1 for halfwords, and cas0:3 for fullwords. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 0 0 0 0 01 xx 0 x xxxx transfer direction transfer width transfer mode peripheralsetup peripheral wait peripheral hold bit 2 bits 4:5 bits 9:10 bits 11:12 bits 13:18 bits 19-21 1 10 01 note 3 xx xxxx xxx 1 sysclk dmar dmaa a11:29 r/w ras cas0:3 dramoe dramwe d0:31 2 3 4 5 6 7 8 9 10 11 12 s=0 s=1 s=2 sync sync biu req ras cas cas pre- charge row column data (s = peripheral setup time)
ibm powerpc 403gb 41 dma fly-by continuous burst to 3-cycle dram bank register bit settings dma control register bit settings notes: 1. dmar must be inactive at the end of cycle 9 (last dmaa cycle) to guarantee three transfers. 2. peripheral data bus width must match dram bus width. 3. see diagram for settings. 4. this waveform assumes that the internal address mux is used. 5. cas0 is used for byte accesses, cas0:1 for halfwords, and cas0:3 for fullwords. 6. numbers ( 1 , 2 , 3 ,...) in the dmar signal represent when dmar is sampled and accepted. numbers ( 1 , 2 , 3 ,...) in the dmaa signal represent the transfers associated with the accepted dmar . slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 0 0 0 1 01 01 0 x xxxx transfer direction transfer width transfer mode peripheral setup peripheral wait peripheral hold burst mode bit 2 bits 4:5 bits 9:10 bits 11:12 bits 13:18 bits 19-21 bit 25 1 10 01 note 3 xx xxxx xxx 1 1 sysclk dmar dmaa a11:29 r/w ras cas0:3 dramoe dramwe d0:31 2 3 4 5 6 7 8 9 10 11 12 s=0 s=1 (s = peripheral setup time) dmadxfer sync sync biu req ras cas cas cas cas cas cas pre- charge row column1 column2 column3 data1 data2 data3 1 2 3 1 1 1 2 2 3 3
ibm powerpc 403gb 42 external master nonburst dram read with holdreq/holdack bank register bit settings notes: 1. xsize1 is multiplexed with oe 2. a6, a7, a30, and a31 are multiplexed with wbe0 , wbe1 , wbe2 , and wbe3 , respectively. external master drives a6:7 into the 403gb. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 1 0 0 0 01 xx 0 x xxxx sysclk r/w rasx cas0:3 dramoe dramwe d0:31 1 2 3 4 5 6 7 8 9 10 11 12 amuxcas ras cas pre- charge cas holdreq holdack xsize0:1 1 xreq bsel ext bus master dram control 10 valid address - ext master 403 address 403 data hiz hiz 403 master 403 master dram drives bus a6:31 2 xreq xack
ibm powerpc 403gb 43 external master dram burst write, 3-2-2-2 page mode bank register bit settings notes: 1. xsize1 is multiplexed with oe . 2. xsize0:1 = 11 indicates a burst transfer at the width of the dram device. 3. the burst is terminated in cycle 12 by deasserting the xreq input signal. a burst may also be terminated by deas- serting either xsize0 or xsize1. 4. a6, a7, a30, and a31 are multiplexed with wbe0 , wbe1 , wbe2 , and wbe3 , respectively. external master drives a6:7 in the 403gb. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 1 0 0 1 01 01 0 x xxxx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 sysclk r/w rasx cas0:3 dramoe dramwe d0:31 amuxcas holdreq holdack xsize0:1 1,2,3 ext bus master dram control ras cas pre- charge cas xreq bsel cas cas cas cas cas cas 11 11 11 valid address1 - ext master valid data1 - ext master address2 address3 address4 data2 data3 data4 a6:31 4 xreq 3 xack 17 18
document no. mpr4gbdsu-?1 01.12.95 ? copyright ibm corporation 1996,1997. all rights reserved. printed in the usa on recycled paper. 9-97 ibm microelectronics, powerpc, powerpc architecture, and 403gb are trademarks, ibm and the ibm logo are registered trademarks of ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility of liability for any use of the information contained herein. nothing in this docu- ment shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including but not limited to the implied warran- ties of merchantability or fitness for a particular purpose, are offered in this document. ibm microelectronics division 1580 route 52, bldg. 502 hopewell junction, ny 12533-6531 tel: (800) powerpc

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